1. Field of the Invention
The present invention relates to a column selection circuit of a semiconductor memory such as a DRAM, VRAM or the like which enables high speed reading.
2. Description of the Related Art
As shown schematically in FIG. 3, a conventional column selection circuit of a semiconductor memory is comprised of a column decoder 4 to which a column address signal COL is input and a plurality of column select gate pairs 5-1 and 5-2 (only one pair is shown in FIG. 3) for connecting a pair of bit lines B and B forming a column, when selected by the column decoder 4, to a pair of internal bus lines D and D. Bit lines B and B and internal bus lines D and D are precharged at a predetermined potential V.sub.Bp which is set between low and high potentials.
The reading operation of data stored in a memory cell will be explained referring to FIG. 4.
When a row address signal ROW is applied to a row decoder 2 at timing T7, a word line WL becomes high at timing T8 and information stored in the memory cell 1 appears as a small differential potential between bit lines B and B. A sense amplifier 3 connected between bit lines B and B is driven by a sense amplifier driving signal SADR at timing T9 to amplify potentials of bit lines B and B. These potentials of bit lines B and B are amplified to "high" and "low" due to an amplifying operation of the sense amplifier 3, respectively but potentials of internal bus lines are kept at the precharged potential in this stage.
Next, restriction on the timing of a column address signal COL is explained referring to FIG. 5. As shown in FIG. 5, a minimum time interval between drops of RAS and CAS which are external control signals for the memory is regulated by tRCD (RAS -CAS delay). Since sense amplifier driving signal SADR is generated by delaying RAS, column address signal COL may be fetched into before driving the sense amplifier by sense amplifier driving signal SADR if tRCD is minimum. However, if column select gates 5-1 and 5-2 are opened at a timing earlier than a start of the drive operation by the sense amplifier 3, a differential potential between bit lines B and B becomes smaller than the initial differential potential since stray capacitances of internal bus lines D and D are usually far larger than those of bit lines B and B and, accordingly, potentials of bit lines B and B are not amplified effectively. In order to avoid this problem, time margin t1 is defined so that a column address signal COL is applied to open column select gates 5-1 and 5-2 after a differential potential between bit lines B and B becomes reasonably large due to an amplifying operation of the sense amplifier.
Returning to FIG. 4, when a column address signal COL is input to column decoder 4 at timing T10, column select gates 5-1 and 5-2 are opened to connect bit lines B and B to internal data bus lines D and D, respectively.
Thereafter, potentials of bit lines B and B and internal data bus lines D and D are amplified to high and low potentials by sense amplifier 3, respectively, and thereby, one reading operation from memory cell 1 to internal data bus D and D is completed.
In the composition of the conventional column selection circuit, the column selection operation can not be carried out at an earlier timing since a time margin t1 is needed as mentioned above.
Further, if a noise signal is applied to bit lines B and B before the differential potential therebetween is amplified to a reasonably large value, potentials of bit lines B and B become close to each other as indicated by a small circle in FIG. 4, resulting in an error operation and/or delay of amplification operation by the sense amplifier. Also, since faculty of the sense amplifier temporarily decreases due to reduction of the differential potential between bit lines B and B, charge and discharge of the internal data bus lines D and D are slowed down resulting in substantial restrictions to the realization of a stable and high speed reading operation.